This invention relates to a digital processing circuit comprising test registers.
It concerns more particularly a digital circuit having a host interface which provides access from the bus of said digital circuit to an external data processing system.
Test registers are widely used in digital processing circuits and allow the operation of the circuit, particularly that of certain blocks, to be checked during both development and production testing of said circuits.
Up to now, these circuits have only generally provided access to the circuit's operating data, and do not allow the circuits different registers to be individually accessed.
Moreover, these known test registers do not allow a given block to be supplied with predetermined data according to the testing required.
Techniques for transmitting and storing digitized pictures make it possible to significantly improve the quality of the final pictures obtained, as compared to analog transmission. The applications of these techniques can also therefore be multiplied.
However, direct transmission and storage of moving digitized pictures requires an extremely high bit rate which in practice calls for these pictures to be compressed and coded. The digitized pictures are therefore coded prior to transmission so as to reduce the amount of data that they represent, and decoded after transmission.
The coding and decoding techniques are of course crucial to the final picture quality obtained, and it became apparent that some standardization would be required to ensure compatibility between the different equipment using these techniques.
Accordingly, a group of experts (known as the Moving Picture Expert Group or "MPEG") drew up the ISO Standard 11172. This standard, often referred to as MPEG, defines coding and decoding conditions of moving pictures, possibly associated with a sound signal, which can be used for storing and recalling pictures from memory and transmitting them.
This MPEG standard can be used to store pictures on compact discs, interactive compact discs, magnetic tapes, and to transmit pictures over local area networks and telephone lines as well as to transmit TV pictures through the air. For a full, detailed description of the entire technique, the reader is invited to read the MPEG standards which are referenced below.
Compressing data according to the MPEG standard may follow several different procedures. Consecutive pictures are collected making up a group of images forming a sequence. A sequence is therefore subdivided into groups of images. Each image is divided into sections and each section is broken down into macro-blocks which constitute the base element used to apply movement compensation and to change, where necessary, the quantization scale.
The macro-blocks are formed from a 16.times.16 matrix of picture elements (pixels). Each macro-block is divided into six blocks, the first four blocks carrying a brightness signal, and the other two blocks a chrominance signal, respectively blue and red. Each of these six blocks is defined as an 8.times.8 matrix of picture elements (pixels). Given the analogies existing between the information contained in the different images in a given sequence and in order to reduce the quantity of information stored or transmitted, different types of image are defined within each sequence.
I pictures (Intra frames) are pictures which are coded as a still image and therefore without reference to another image.
P images (Predicted) are deduced starting from the I or P image previously reconstructed.
B images (Bi-directional frames) are deduced from two reconstructed images, one I and one P or two P, one just before and the other just after.
It should be stressed that the images in a sequence are transmitted in the order of decoding and not generally in the order in which they are presented at the time of acquisition or restitution.
The Discrete Cosine Transformation (DCT) is applied on the block level. This DCT transformation transforms the spatial blocks, defined as indicated above as an 8.times.8 matrix of pixels, into temporal blocks formed also as an 8.times.8 matrix, of spatial frequencies.
It has been found that in the 8.times.8 matrix of the temporal block, the continuous background coefficient (DC) placed in the upper left hand corner of the matrix is much more important in terms of the visual impression obtained than the other components corresponding to different frequencies.
More precisely, the higher the frequency, the less sensitive the eye is to it. This is why the levels of frequencies are quantized, especially since the frequencies are high. This quantization is ensured by an algorithm that is not imposed by the standard, and which could be a quantization and variable length coding (VLC) operation.
The matrix in the frequency domain obtained by the DCT transformation is next processed by a matrix called "quantization matrix" which is used to divide each of the terms of the matrix of the temporal domain by a value that is linked to its position, and which takes account of the fact that the weight of the different frequencies presented by these coefficients is variable.
After each value has been rounded to the closest integer value, this operation results in a large number of coefficients equal to zero.
It should be stressed that for the intra macro-blocks, the quantization value of the DC coefficient is constant, for example 8. The non-zero frequency coefficients are then coded according to zigzag type scanning with reference to a Huffman table, which gives a variable-length coded value to each of the coefficients of the matrix and reduces the volume. Preferably, the coefficients representing the continuous backgrounds are transmitted after quantization and, in addition, the quantization matrix is optimized, in such a way that the volume of data is under a predetermined level which corresponds to the maximum storage or transmission possibilities, without any serious reduction in the quality of information transmitted.
Type I frames are coded without use of the movement vector. Conversely, P and B frames use movement vectors, at least for certain macro-blocks which make up these frames, allowing coding efficiency to be increased and indicating from which part of the reference image(s) a particular macro-block of the considered frame must be deduced.
The search for the movement vector is the object of optimization at the time of coding, and the movement vector is itself coded by using the DPCM technique, which best exploits the existing correlation between the movement vectors of the different macro-blocks of a given image. They are finally the object of variable-length coding (VLC).
All the data concerning a coded sequence form the bit stream that is either recorded or transmitted. Such a bit stream begins with a sequence header containing a certain amount of information and parameters whose values are maintained throughout the sequence.
Likewise, the sequence is broken down into groups of frames, each of these groups is preceded by a group header and the data representing each frame are themselves preceded by a frame header.
The implementation of test registers is particularly important in complex circuits such as those used to decode bit streams for the reconstruction of pictures of the kind envisaged by the MPEG standard.
A first object of the invention is to allow a block to be tested inside a digital processing circuit by choosing the input data and examining the output data from this block.
Another object of this invention is to allow tests to be conducted using registers which can be transparent when the system is in use.
A further object of the invention is to allow test registers to be used within the context of the development of MPEG decoding circuits allowing setting of parameters representative of the operating environment of the system, such as size and other representative parameters of an image.
The invention concerns a digital processing circuit containing a host interface providing access from its bus to an external data processing system, said processing circuit being broken down into blocks, and having test registers interposed between an upstream block and downstream block.
According to the invention, the test registers are connected to the bus and identified by an address allowing data to be sent to them or read from them.
In different preferred embodiments, the device of the invention comprises the following characteristics taken in any technically feasible combination:
each register has an active state, when the register will detect orders from the bus, and a rest state, when it will not, said bus comprising control lines, an address line and data lines, the test registers comprising means for generating write signals according to the signals present on these lines making it pass to the active state, and additional means authorizing this write or read operation;
the test registers are transparent in the rest state;
it comprises a first multiplexer commanded by the write signal, receiving on one of its inputs the data flowing across the bus, the output of said multiplexer being connected to a second multiplexer commanded by the output of a logic operator which receives on input the write signal and a write enable signal, the second input of said second multiplexer being connected to the upstream block and the output of said second multiplier to the downstream block in the rest state, the test registers behave like a D-type flip-flop; each test register comprises a D-type flip-flop placed between the blocks, said blocks being separated by the register when it is in the rest state;
it allows operating tests to be conducted on a block n at nominal speed, the input test vector being written into the upstream register on the positive-going transition of a first clock pulse, the downstream register being read on the positive-going transition of a second clock pulse immediately following the first;
before the start of a read or write cycle, the impedance of the data bus is high;
it is included in a unit for decoding a bit stream representing pictures complying with the MPEG Standard;
a given test register can maintain the active state indefinitely, with access to the other test registers still being authorized;
at least one test register contains the information of its own state (active or at rest);
a test register can be activated by a program in the application environment, while all the other blocks in the circuit that are not concerned continue to behave normally.